Quick Navigation Bar
advanced data structures :: make and makefiles :: debugging techniques
[ toc | forums ]

Note: If the document URL does not begin with https://randu.org/tutorials/c/ then you are viewing a copy. Please direct your browser to the correct location for the most recent version.

Make and Makefiles Overview

Make allows a programmer to easily keep track of a project by maintaining current versions of their programs from separate sources. Make can automate various tasks for you, not only compiling proper branch of source code from the project tree, but helping you automate other tasks, such as cleaning directories, organizing output, and even debugging.

Make and Makefiles :: An Introduction

If you had a program called hello.c, you could simply call make in the directory, and it would call cc (gcc) with -o hello option. But this isn't why make is such a nice tool for program building and management.
The power and ease of use of make is facilitated through the use of a Makefile.
Make parses the Makefile for directives and according to what parameters you give make, it will execute those rules.
Rules take the following form:
```
target target_name : prerequisites ...
        command
        ...
```
The target is the parameter you give make. For example make clean would cause make to carry out the target_name called clean. If there are any prerequisites to process, they make will do those before proceeding. The commands would then be executed under the target.
NOTE: The commands listed must be TABBED over!

Examples? The following Makefile below is a very simple one taken from the GNU make manual:

edit : main.o kbd.o command.o display.o insert.o search.o files.o utils.o
        cc -o edit main.o kbd.o command.o display.o insert.o search.o \
	files.o utils.o

main.o : main.c defs.h
        cc -c main.c
kbd.o : kbd.c defs.h command.h
        cc -c kbd.c
command.o : command.c defs.h command.h
        cc -c command.c
display.o : display.c defs.h buffer.h
        cc -c display.c
insert.o : insert.c defs.h buffer.h
        cc -c insert.c
search.o : search.c defs.h buffer.h
        cc -c search.c
files.o : files.c defs.h buffer.h command.h
        cc -c files.c
utils.o : utils.c defs.h
        cc -c utils.c
clean :
        rm edit main.o kbd.o command.o display.o insert.o search.o \
	files.o utils.o

Now if you change just kbd.c, it will only recompile kbd.c into it's object file and then relink all of the object files to create edit. Much easier than recompiling the whole project!

But that's still too much stuff to write! Use make's smarts to deduce commands. The above example re-written (taken from GNU make manual):
```
objects = main.o kbd.o command.o display.o insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h

.PHONY: clean
clean :
        rm edit $(objects)
```
So what changed? Now we have a grouping of objects containing all of our object files so that the edit target only requires this variable. You may also notice that all of the .c files are missing from the prerequisite line. This is because make is deducing that the c source is a required part of the target and will automatically use the c source file associated with the object file to compile. What about the .PHONY target? Let's say you actually have a file called "clean". If you had just a clean target without the .PHONY, it would never clean. To avoid this, you can use the .PHONY target. This isn't used that often because it is rare to have a file called "clean" in the target directory... but who knows if you might have one?

Make and Makefiles :: Beyond Simple

You can include other Makefiles by using the include directive.
You can create conditional syntax in Makefiles, using ifdef, ifeq, ifndef, ifneq.
You can create variables inside of Makefiles, like the $(objects) above.

Let's use a different example. The hypothetical source tree:

                            moo.c
                            /   \
                         ---     ---
                        /           \
                      foo.c        bar.c
                      /               \
                  -------           -------
                 /       \         /       \
              baz.c    loop.h   dood.c   shazbot.c
               /                             \
           -------                        -------
          /       \                      /       \
        mop.c  <libgen.h>             woot.c   defs.h

Let's create a more complex, yet easier to maintain Makefile for this project:

# Source, Executable, Includes, Library Defines
INCL   = loop.h defs.h
SRC    = moo.c foo.c bar.c baz.c dood.c shazbot.c mop.c woot.c
OBJ    = $(SRC:.c=.o)
LIBS   = -lgen
EXE    = moolicious

# Compiler, Linker Defines
CC      = /usr/bin/gcc
CFLAGS  = -ansi -pedantic -Wall -O2
LIBPATH = -L.
LDFLAGS = -o $(EXE) $(LIBPATH) $(LIBS)
CFDEBUG = -ansi -pedantic -Wall -g -DDEBUG $(LDFLAGS)
RM      = /bin/rm -f

# Compile and Assemble C Source Files into Object Files
%.o: %.c
       $(CC) -c $(CFLAGS) $*.c

# Link all Object Files with external Libraries into Binaries
$(EXE): $(OBJ)
       $(CC) $(LDFLAGS) $(OBJ)

# Objects depend on these Libraries
$(OBJ): $(INCL)

# Create a gdb/dbx Capable Executable with DEBUG flags turned on
debug:
       $(CC) $(CFDEBUG) $(SRC)

# Clean Up Objects, Exectuables, Dumps out of source directory
clean:
       $(RM) $(OBJ) $(EXE) core a.out

Now we have a clean and readable Makefile that can manage the complete source tree. (Remember to use tabs on the command lines!)

You can manipulate lots and lots of things with Makefiles. I cannot possibly cover everything in-depth in this short tutorial. You can navigate between directories (which can have separte Makefiles/rules), run shell commands, and various other tasks with make.

Make and Makefiles :: Where to go from here?

A lot of this tutorial references the GNU make manual. If you have any questions about Make, the GNU manual should cover it.
GNU autoconf is a tool for automatically generating configure files from a configure.in file. These configure files can automatically setup Makefiles in conjunction with GNU automake and GNU m4. These tools are way beyond the scope of this document. Look in GNU's manual repository for more information on these tools.
CVS is another tool that may be useful for very large projects. CVS stands for Concurrent Versions System and it allows you to record the history of your source files. CVS stores the base source and then stores the differences for each version. CVS also allows for protecting code pieces of a multi-developer effort from accidental overwriting... in other words, code-insulation. More information on CVS can be found here.

Notice: Please do not replicate or copy these pages and host them elsewhere. This is to ensure that the latest version can always be found here.

Disclaimer: The document author has published these pages with the hope that it may be useful to others. However, the document author does not guarantee that all information contained on these webpages are correct or accurate. There is no warranty, expressed or implied, of merchantability or fitness for any purpose. The author does not assume any liability or responsibility for the use of the information contained on these webpages.

If you see an error, please send an email to the address below indicating the error. Your feedback is greatly appreciated and will help to continually improve these pages.